1. Field
The embodiments discussed herein are relates to a method and apparatus for peeling an electronic component.
2. Description of the Related Art
In a process of manufacturing a semiconductor device such as a semiconductor integrated circuit device, a so-called dicing process (segmentation process) is performed to separate multiple semiconductor elements (semiconductor integrated circuit elements), which are formed on a single piece of semiconductor substrate (wafer) through a so-called wafer process, into multiple pieces.
That is, in the process of manufacturing a semiconductor device, multiple semiconductor elements, each having an electronic circuit formed of an active element such as a transistor, a passive element such as a resistance element or a capacitive element, and a wiring layer that connects these functional elements on one of main surfaces of a semiconductor substrate such as a silicon (Si), are formed through a so-called wafer process.
Then, a grinding process is performed on the other surface (rear surface, on which no electronic circuit is formed) of the semiconductor substrate to reduce the thickness of the semiconductor substrate.
Furthermore, a so-called dicing process is performed on the semiconductor substrate, so that the semiconductor substrate is separated (segmented) into the individual semiconductor elements.
Each of the segmented semiconductor elements (semiconductor chips) is transported directly or transported with placed on a tray, or the like, mounted on a support member such as a wiring substrate or a lead frame, and then connected to an electrode or a lead wire and sealed, thus forming a semiconductor device.
In the manufacturing process, the dicing process fixes the other main surface of a processed semiconductor substrate by adhering the other main surface onto a tape whose surface is adhesive and, in the above state, separates (segments) the semiconductor substrate into separate semiconductor elements through a dicing blade method or a laser dicing method.
Note that the tape that is employed in the dicing process is called a dicing tape; however, another method in which a dicing tape is not adhesive and a semiconductor substrate is fixed onto the dicing tape through an adhesive tape may be employed.
The segmented semiconductor element is pressed (pushed up) with a pressing jig from the rear surface of the dicing tape while the upper surface of the semiconductor element is vacuumed and held by a vacuum jig (vacuum collet), thus being peeled off from the dicing tape.
The semiconductor element held by the vacuum jig is, for example, placed on a transport tray as described above and then transported to the next process such as a mounting process to a circuit substrate.
In an existing art, a processing method and processing apparatus for picking up the semiconductor elements from the dicing tape after the dicing process employ the configuration shown in FIG. 1, for example.
That is, a dicing tape 21 to which multiple semiconductor elements 1 that are segmented through the dicing process are adhered is set to a processing apparatus 100, and the semiconductor element is pushed up from the rear surface of the dicing tape 21 by a push-up jig 3 one by one. This reduces an area in which the semiconductor element 1 is adhered to the dicing tape 21.
In addition, in association with the push-up operation, the semiconductor element 1 is vacuumed and held by a vacuum jig (vacuum collet) 4 at its upper surface and is raised, thus being peeled from the dicing tape 21.
The push-up jig 3 has a flat portion 31 that has dimensions substantially corresponding to the outside dimensions of the semiconductor element 1 and a cylindrical wall portion 32 that surrounds the flat portion. The flat portion 31 has a plurality of through-holes 33.
Then, in correspondence with the through-holes 33, a plurality of needles 34 are held by a needle support portion 35 so as to be movable vertically (indicated by arrow P). In a state where the flat portion 32 is in contact with the dicing tape 21, vacuuming is performed through the through-holes 33 to thereby fix the dicing tape 21.
In such a state, the needle support portion 35 is raised to make the needles 34 pass through the through-holes 33 and then press the dicing tape 21 or extend through the dicing tape 21 to thereby press the rear surface of the semiconductor element 1.
On the other hand, in correspondence with the push-up jig 3, a vacuum jig 4 is arranged above the target semiconductor element 1 so as to be movable vertically (indicated by arrow Q).
The vacuum jig 4 may also be called a vacuum collet, and a vacuum opening 41 thereof is connected to a vacuum suction device (not shown).
In the processing apparatus 100, a process of peeling the semiconductor element 1 from the dicing tape 21 is performed as follows.
That is, the target semiconductor element 1 held on the dicing tape 21 is located directly above the push-up jig 3, and the vacuum jig 4 is located directly above that semiconductor element 1.
Subsequently, the push-up jig 3 is placed in proximity to the dicing tape 21, the dicing tape 21 is vacuumed through the through-holes 33 formed in the push-up jig 3 to thereby fixes the dicing tape 21 on the flat portion 31.
In such a state, the needle support portion 35 is raised, to make the needles 34 pass through the through-holes 33 and then press the dicing tape 21 or extend through the dicing tape 21 to thereby press the rear surface of the semiconductor element 1.
Thus, the semiconductor element 1 is peeled off from the surface of the dicing tape 21.
In association with the peeling operation, the vacuum jig 4 is lowered and vacuums the semiconductor element 1 through the vacuum opening 41, and then the vacuum jig 4 is raised while holding the semiconductor element 1.
Then, the vacuum jig 4 transports the semiconductor element 1 to a transport tray, and the like.
Japanese Laid-open Patent Publication No. 11-297793 discloses push-up manners using the plurality of needles, push-up pins located at substantially the center portion of the semiconductor element and push-up pins located around the center push-up pins are pushed up (pressed up) at a time interval to thereby make it easy to peel the semiconductor element from the dicing tape. In addition, Japanese Laid-open Patent Publication No. 6-85060 discloses another means, an adhesive sheet on the upper surface of which multiple semiconductor elements are adhered is tensioned to a stretched ring, each of the multiple semiconductor elements is pressed by a pressing block having a planar pressing surface from the lower surface of the adhesive sheet without breaking the adhesive sheet to thereby peel the individual semiconductor elements from the adhesive sheet. Furthermore, Japanese Laid-open Patent Publication No. 2007-109936 discloses further another means, the semiconductor element is pressed from the rear surface of an adhesive sheet, on the upper surface of which multiple semiconductor elements are adhered, using a sheet pressing member formed of a flexible elastic body such as rubber formed in a spherical shape without breaking the adhesive sheet, to thereby peel the individual semiconductor elements from the adhesive sheet.
The process of peeling the semiconductor element 1 from the dicing tape 21 in the processing apparatus 100 shown in FIG. 1 performs pressing the back surface of the target semiconductor element 1 with the plurality of needles 34.
Thus, the semiconductor element 1 will have portions that are directly pressed by the needles 34 and portions that are not pressed by the needles 34. This provides a state in which the semiconductor element 1 is peeled nonuniformly from the dicing tape 21 and, as a result, it is likely that the contact surface of the semiconductor element 1 with the dicing tape 21 is peeled nonuniformly.
For this reason, a peeled form is unstable and, therefore, the semiconductor element 1 may not be vacuumed and held by the vacuum jig 4.
In addition, according to the above means, it is necessary that the positions (levels) of the distal end portions of the plurality of needles 34 are equal. That is, if the positions of the distal end portions of the plurality of needles 34 are not equal due to abrasion or bending of the distal end portions, it is difficult to apply a uniform pressing force to the contact surface of the target semiconductor element 1 with the dicing tape 21.
In this way, if the positions of the distal end portions of the plurality of needles 34 are not equal, cracking, or the like, may possibly arise in the semiconductor element 1.
Moreover, it is extremely difficult to visually inspect the condition of the distal end portions of the plurality of needles 34. Thus, in the processing apparatus 100 having the above configuration, it is difficult to stably perform the process of peeling the semiconductor element 1 from the dicing tape 21.
The above problem also applies to the technology described in Japanese Laid-open Patent Publication No. 11-297793 that similarly uses a plurality of push-up pins.
In addition, in the technology described in Japanese Laid-open Patent Publication No. 11-297793, because push-up (pressing) operation is performed at a time interval between push-up pins that are located at substantially the center portion of the semiconductor element and push-up pins that are located around substantially the center portion, it may be easy to peel the semiconductor element from the dicing tape; however, there still exits the influence on the semiconductor element due to the shape of the distal end of the push-up pin, nonuniform positions of the distal end portions, and the like.
On the other hand, in the technology described in Japanese Laid-open Patent Publication No. 6-85060, the process of peeling the semiconductor element from the dicing tape is performed using a pressing block on the upper surface of which a plurality of cones are arranged or a pressing block whose upper surface forms a polyhedron; however, an area in which the dicing tape is in contact with the semiconductor element is large even after the push-up operation and, therefore, it is difficult to peel the semiconductor element.
Then, in the technology described in Japanese Laid-open Patent Publication No. 2007-109936, a sheet pressing member formed of a flexible elastic body in a spherical shape is used, the process of peeling a chip from the sheet is performed so that the sheet pressing member elastically deforms, that is, the upper surface of the sheet pressing member deforms from a flat surface to a spherical surface.
At this time, in the above processing method, when the upper surface of the sheet pressing member is changed from a spherical shape to a flat surface in advance, a porous vacuum plate of a pick-up nozzle is brought into contact with a chip and a pressure is applied to a sheet pressing member across a sheet located beneath the chip. That is, at the time of initiation of pressurization, the chip is pressed by the sheet pressing member with an extremely small area. Thus, particularly when a chip has a relatively large area and a small thickness, cracking or chipping is likely to arise in the chip.
On the other hand, in response to a request for miniaturization and high performance of an electronic apparatus, further high performance is also required for the semiconductor element 1. This increases a chip size, whereas a further reduction in thickness of the chip, that is, a thin chip, is sought.
In this way, when a semiconductor element that is thinned while being increased in size (increased in area) and, as a result, decreased in mechanical strength is peeled from the dicing tape, a further careful execution of the peeling process is necessary so as not to bring about a breakage.